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MAX11130 Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX11130 Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 36 page ����������������������������������������������������������������� Maxim Integrated Products 8 MAX11129–MAX11132 3Msps, Low-Power, Serial 12-/10-Bit, 8-/16-Channel ADCs ELECTRICAL CHARACTERISTICS (MAX11129/MAX11130) (continued) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 3Msps, fSCLK = 48MHz, 50% duty cycle, VREF+ = VDD, TA= -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) Note 2: Limits are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design. Note 3: Channel ID disabled. Note 4: Tested in single-ended mode. Note 5: Offset nulled. Note 6: Line rejection D(DOUT) with VDD = 2.35V to 3.6V and VREF+ = 2.35V. Note 7: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle. Maximum conversion time: 1.91Fs + N x 16 x TOSC_MAX TOSC_MAX = 29.4ns, TOSC_TYP = 25ns. Note 8: The operational input voltage range for each individual input of a differentially configured pair is from VDD to GND. The operational input voltage difference is from -VREF+/2 to +VREF+/2 or -VREF+ to +VREF+. Note 9: See Figure 3 (Equivalent Input Circuit). Note 10: Guaranteed by characterization. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (Figure 1) (Note 10) SCLK Clock Period tCP Externally clocked conversion 20.8 ns SCLK Duty Cycle tCH 40 60 % SCLK Fall to DOUT Transition tDOT CLOAD = 10pF VOVDD = 1.5V to 2.35V 4 16.5 ns VOVDD = 2.35V to 3.6V 4 15 16th SCLK Fall to DOUT Disable tDOD CLOAD = 10pF, channel ID on 15 ns 14th SCLK Fall to DOUT Disable CLOAD = 10pF, channel ID off 16 SCLK Fall to DOUT Enable tDOE CLOAD = 10pF 14 ns DIN to SCLK Rise Setup tDS 4 ns SCLK Rise to DIN Hold tDH 1 ns CS Fall to SCLK Fall Setup tCSS 4 ns SCLK Fall to CS Fall Hold tCSH 1 ns CNVST Pulse Width tCSW See Figure 6 5 ns CS or CNVST Rise to EOC Low (Note 7) tCNV_INT See Figure 7, fSAMPLE = 3Msps 2.1 2.4 F s CS Pulse Width tCSBW 5 ns |
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