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MAX11129–MAX11132

3Msps, Low-Power, Serial 12-/10-Bit,

8-/16-Channel ADCs

ELECTRICAL CHARACTERISTICS (MAX11129/MAX11130) (continued)

Note 3: Channel ID disabled.

Note 4: Tested in single-ended mode.

Note 5: Offset nulled.

Note 7: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.

Note 9: See Figure 3 (Equivalent Input Circuit).

Note 10: Guaranteed by characterization.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (Figure 1) (Note 10)

SCLK Clock Period

Externally clocked conversion

20.8

ns

SCLK Duty Cycle

40

60

%

SCLK Fall to DOUT Transition

10pF

4

16.5

ns

4

15

16th SCLK Fall to DOUT Disable

15

ns

14th SCLK Fall to DOUT Disable

16

SCLK Fall to DOUT Enable

14

ns

DIN to SCLK Rise Setup

4

ns

SCLK Rise to DIN Hold

1

ns

CS Fall to SCLK Fall Setup

4

ns

SCLK Fall to CS Fall Hold

1

ns

CNVST Pulse Width

See Figure 6

5

ns

CS or CNVST Rise to EOC Low

(Note 7)

2.1

2.4

F

s

CS Pulse Width

5

ns