Figure 2. FUNCTIONAL BLOCK DIAGRAM

REF

B

C

GND

-V

DATA (A)

DATA (B)

SYNC

CLOCK

STROBE

A

C

V

+V

LEVEL SHIFTER

AND SLOPE

CONTROL (B)

LEVEL SHIFTER

AND SLOPE

CONTROL (A)

CURRENT

REGULATOR

OUTPUT

DRIVER (A)

OUT

B

OUT

A

OUTPUT

DRIVER (B)

R/ 2

OUT

R/ 2

OUT

Not included on HI-8383

OVER VOLTAGE

CLAMPS

DATA (A)

OUT

DATA (B)

INPUTS

TO ARINC BUS

A

OUT

B

REF

V

1

V

SYNC

CLOCK

-V

+V

STROBE

GND

B

A

C

C

-15V

+15V

+5V

The SYNC and CLOCK inputs establish data synchronization

utilizing two AND gates, one for each data input. Each logic

input, including the power enable (

) input, are

TTL/CMOS compatible. Besides reducing chip current drain,

also floats each output. However the overvoltage

fuses and diodes of the HI-8382 are not switched out.

Figure 1 illustrates a typical ARINC 429 bus application.

Three power supplies are necessary to operate the HI-8382;

typically +15V, -15V and +5V. The chip also works with ±12V

supplies. The +5V supply can also provide a reference

voltage that determines the output voltage swing.

The

differential output voltage swing will equal 2V

. If a value of

V

other than +5V is needed, a separate +5V power supply

is required for pin V .

With the DATA (A) input at a logic high and DATA (B) input at a

logic low, A

will switch to the +V

rail and B

will

switch to the -V

rail (ARINC HIGH state). With both data

input signals at a logic low state, the outputs will both switch to

0V (ARINC NULL state).

The driver output impedance, R

, is nominally 75 ohms.

The rise and fall times of the outputs can be calibrated through

the selection of two external capacitor values th

re

connected to the C and C input pins. Typical values for

high-speed operation (100KBPS) are C = C = 75pF and for

low-speed operation (12.5 to 14KBPS) C = C = 500pF.

STROBE

STROBE

REF

REF

OUT

REF

OUT

REF

OUT

1

AB

AB

AB

at a

The driver can be externally powered down by applying a logic

high to the

input pin. If this feature is not being used,

the pin should be tied to ground.

The C

and C

pins are inputs to unity gain amplifiers.

Therefore they must be allowed to swing to -5V. Provision to

STROBE

AB

switch capacitors must be done with analog switches that

allow voltages below their ground.

The power supplies should be controlled to prevent large

currents during supply turn-on and turn-off. The recom-

mended sequence is +V followed by V , always ensuring that

+V is the most positive supply. The -V supply is not critical

and can be asserted at any time.

Both ARINC outputs of the HI-8382 are protected by internal

fuses capable of sinking between 800 - 900 mA for short

periods of time (125µs).

POWER SUPPLY SEQUENCING

1

Figure 1. ARINC 429 BUS APPLICATION

FUNCTIONAL DESCRIPTION

HI-8382, HI-8383

HOLT INTEGRATED CIRCUITS

2