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F28M35H20B1_1110 Datasheet(PDF) 6 Page - Texas Instruments |
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F28M35H20B1_1110 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 104 page  F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742B – JUNE 2011 – REVISED OCTOBER 2011 www.ti.com LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS Section 2.4.4 Updated "C28x Local Peripherals" section Section 2.4.6 Updated "C28x Accessing Shared Resources and Analog Peripherals" section Section 2.5 Updated "Analog Subsystem" section Section 2.5.1 Updated "ADC1" section Section 2.5.2 Updated "ADC2" section Figure 2-3 Updated "Analog Subsystem" figure Section 2.5.3 Updated "Analog Comparator + DAC" section Section 2.5.4 Updated "Analog Common Interface Bus (ACIB)" section Section 2.6 Updated "Master Subsystem NMIs" section Section 2.7 Updated "Control Subsystem NMIs" section Figure 2-4 Updated "Cortex ™-M3 NMI and C28x NMI" figure Section 2.8 Updated "Resets" section Section 2.8.1 Updated "Cortex ™-M3 Resets" section Figure 2-5 Updated "Resets" figure Section 2.8.4 Added "Device Boot Sequence" section Section 2.9 Updated "Master Subsystem Clocking" section Table 2-19 Added "Master Subsystem Low-Power Modes" table Figure 2-6 Updated "Cortex ™-M3 Clocks and Low-Power Modes" figure Section 2.9.1 Updated "Cortex ™-M3 Run Mode" section Section 2.9.2 Updated "Cortex ™-M3 Sleep Mode" section Section 2.9.3 Updated "Cortex ™-M3 Deep Sleep Mode" section Section 2.10 Updated "Control Subsystem Clocking" section Table 2-20 Added "Control Subsystem Low-Power Modes" table Figure 2-7 Updated "C28x Clocks and Low-Power Modes" figure Section 2.10.1 Updated "C28x Normal Mode" section Section 2.10.3 Updated "C28x Standby Mode" section Section 2.11 Updated "Analog Subsystem Clocking" section Section 2.12 Added "Shared Resources Clocking" section Section 2.13 Changed section title from "GPIOs" to "GPIOs and Other Pins" Section 2.13 Updated "GPIOs and Other Pins" section Section 2.13.1 Updated "GPIO_MUX1" section Figure 2-8 Updated "GPIOs and Other Pins" figure Figure 2-9 Added "GPIO_MUX1 Block" figure Figure 2-10 Added "GPIO_MUX1 Pin Mapping Through Register Set A" figure Table 2-21 Added "GPIO_MUX1 Pin Assignments (M3 Primary Modes)" table Table 2-22 Added "GPIO_MUX1 Pin Assignments (M3 Alternate Modes)" table Table 2-23 Added "GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)" table Section 2.13.2 Updated "GPIO_MUX2" section Table 2-24 Added "GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)" table Figure 2-11 Added "Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2" figure Section 2.13.3 Updated "AIO_MUX1" section Table 2-25 Added "AIO_MUX1 Pin Assignments (C28x AIO Modes)" table Section 2.13.4 Updated "AIO_MUX2" section Table 2-26 Added "AIO_MUX2 Pin Assignments (C28x AIO Modes)" table Figure 3-1 144-Pin RFP PowerPAD ™ HTQFP (Top View): • Pin 135: Changed signal name from "ADC2VREFLO" to "ADC2VREFLO, VSSA2" 6 Contents Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback |
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