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OMAPL138BZCE3 Datasheet(PDF) 3 Page - Texas Instruments |
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OMAPL138BZCE3 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 287 page  OMAP-L138 www.ti.com SPRS586C – JUNE 2009 – REVISED MAY 2011 • Two Enhanced Pulse Width Modulators – Configurable as 3 Capture Inputs or 3 (eHRPWM): Auxiliary Pulse Width Modulator (APWM) outputs – Dedicated 16-Bit Time-Base Counter With Period And Frequency Control – Single Shot Capture of up to Four Event Time-Stamps – 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch – Dead-Band Generation • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) – PWM Chopping by High-Frequency Carrier [ZWT Suffix], 0.80-mm Ball Pitch – Trip Zone Input • Commercial, Extended or Industrial • Three 32-Bit Enhanced Capture Modules Temperature (eCAP): 1.2 Description The OMAP-L138 C6-Integra ™ DSP+ARM® processor is a low-power applications processor based on an ARM926EJ-S ™ and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000 ™ platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller. Copyright © 2009–2011, Texas Instruments Incorporated OMAP-L138 C6-Integra ™ DSP+ARM® Processor 3 Submit Documentation Feedback Product Folder Link(s): OMAP-L138 |
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