 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SIC413DB Datasheet(PDF) 11 Page - Vishay Siliconix |
|
||||||||||||||||||||||||||||||
SIC413DB Datasheet(HTML) 11 Page - Vishay Siliconix |
|
|
11 / 18 page  Vishay Siliconix SiC413 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 www.vishay.com 11 Compensation Considerations The criterion for unconditional stability of a closed loop system is that the open loop transfer function has the following attributes. 1. The magnitude of the open loop transfer function must cross through 0 dB with a slope of - 20 dB per decade 2. The phase shift of the open loop transfer function must be at least 45 at the frequency, at which the magnitude of the loop gain crosses through 0 dB 3. The phase shift should not be rapidly decreasing at loop gain slightly less than 0 dB To determine if these criterion are met the Bode plot of the transfer function is drawn. Before drawing the bode plot, the poles and zeros need to be located. The following discussion serves as a guide to selection of the component values for the compensation network. The compensation process begins by selecting loop bandwidth. We recommend that the 0 dB crossover frequency is set somewhere between 10 % and 20 % of switching frequency. The SiC413CB has a fixed switching frequency of 500 kHz. This means that the bandwidth of the loop can be set somewhere between 50 kHz and 100 kHz. This wide loop bandwidth, made possible by the ultra fast error amplifier in the SiC413CB, can provide excellent transient response and load regulation. It can be seen that within the LC filter block, there are generally three poles (denoted P1, P2 and P3) and one zero (denoted Z1). The double pole (P1 and P2) created by the LC filter is the dominant response characteristic of the system. The locations of these poles and zero depend strongly on the types of capacitors used in the output filter. Three cases will be analyzed as follows. Case 1: Output capacitors are a combination of those with ESR (C5. e.g. polymer or tantalum type) and those with no ESR or little ESR (C4. e.g. ceramic type) The poles and zero for this case are as follows To meet the above stability criterion, the frequency of the zero fZ1 should be placed at a frequency lower than or equal to that at the double pole of fP1,P2. Pole fP3 should be located at a much higher frequency than fP1,P2. This requirement sets the boundaries on the values of C4, C5 and R6. Capacitor C4 has to be much smaller than C5. Case 2: Output capacitor is all ceramic MLCC Ignoring C5 and R6, the poles are as follows This output filter configuration can be challenging because there is no zero to help boost the phase shift that is introduced by the LC double pole. Case 3: All capacitors have ESR, no ceramics. Ignoring C4 we have the following for the poles and zero This case is the best situation for loop compensation since no extra pole to add phase shift. The zero created with the ESR also helps reverse phase shift added by the LC filter. In the output voltage feedback network block there is one pole (denoted P4) and one zero (denoted Z2). The locations of the pole and zero are In this block C1 and R1 create the zero and C1 together with the parallel combination of R1 and R2 generates the pole. Adding a capacitor in parallel with R2 is not effective here. It does not change the zero location and move the pole closer to this zero and cancels out its effect on phase margin. From Figure 4 we can derive the DC expression for the output voltage. From this equation and the equations of the pole and zero locations, it can be seen that pole and zero locations of this block have the following relationship This relationship means that when the output voltage VO is approaching the chip reference voltage, VREF, the zero in the sampling network has diminishing effect on boosting the loop phase margin. In other words, the value if adding C1 is more apparent when the output voltage is high relative to VREF and becomes smaller at lower output voltages. Therefore, the use of this capacitor is optional for low voltage conversions (e.g. 1.2 V output or lower). To make the zero fZ2 work for compensation of the control loop it should to be placed at a frequency that is less than or equal to the frequency of the LC double pole location. Block 3 is a DC transfer block and therefore has no pole and zero. It only affects the DC gain of open loop transfer function. This can affect phase margin as increasing the DC loop gain can increase the loop bandwidth and reduce phase margin and visa versa. 2 π 1 L1 • (C4 + C5) fP1,P2 ≈ 2 π • C4 • R6 1 f P3 ≈ 2 π • C5 • R6 1 f Z1 ≈ 2 π 1 L1 • C4 fP1,P2, MLCC = P3, MLCC f and Z1, MLCC f will not exist 2 π 1 L1 • C5 fP1,P2,ESR = P3,ESR f does not exist 2 π • C5 • R6 1 f Z1,ESR = 2 π • C1 • (R1//R2) 1 2 π • 1 R1 + R2 R1 • R2 f P4 = • C1 = 2 π • C1 • R1 1 f Z2 = REF O V R2 R1 V • =) (1 + REF O Z2 P4 V V f f = |
Similar Part No. - SIC413DB |
|
Similar Description - SIC413DB |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
