www.vishay.com

6

Document Number: 73672

S-62656–Rev. C, 25-Dec-06

Vishay Siliconix

SiC734CD9

DEVICE OPERATION

Pulse Width Modulator (PWM)

This is a CMOS compatible logic input that receives the drive

signals from the controller circuit. The PWM signal drives the

buck switch.

Break-Before-Make (BBM)

The SiC730CD9 has an intrenal break-before-make function

to ensure that both high-side and low-side MOSFETs are not

turned on the same time. The low-side MOSFET will not turn

thus ensuring that the high-side MOSFET is turned off. This

parameter is not user adjustable.

SHDN

CMOS logic signal. In the low state, the SHDN disables both

high-side and low-side MOSFET’s.

boot capacitor is used to sustain rail for the high-side MOS-

FET gate drive circuit.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate drive

holding high-side and low-side MOSFET’s low until the input

voltage rail has reached a point at which the logic circuitry

can be safely activated. The UVLO is not user adjustable.

SYNC Pin for Pre-Bias Start-Up

The low side MOSFET can be individually enable or dis-

abled by using the SYNC pin. In the low state (SYNC = low),

the low-side MOSFET is turned off. In the high state, the

low-side MOSFET is enabled and follows the PWM input

signal (see timing diagram, Figure 2). SYNC is a CMOS

compatible logic input and is used for a pre–biased output

voltage.

This is the power input to the drain of the high-side Power

MOSFET. This pin is connected to the high power intermedi-

ate BUS rail.

Switch Node (SW)

The Switch node is the circuit PWM regulated output. This is

the output applied to the filter circuit to deliver the regulated

high output for the buck converter.

Power Ground (PGND)

This is the output connection from the source of the low-side

MOSFET. This output is the ground return loop for the power

rail. It should be externally connected to CGND.

Control Ground (CGND)

This is the control voltage return path for the driver and logic

input circuitry to the SiC730CD9. This should externally con-

nected to PGND.

APPLICATION CIRCUIT

The SiC734CD9 has a built-in delay time that is optimized for

the MOSFET pair. When the PWM signal goes low, the high-

side driver turns on.

When the PWM goes high, the low-side driver turns off,

MOSFET turns on after a short dalay. The delay is minimized

to limit body diode conduction. The output then ramps up,

CGND

5 V

3.3 V to 16 V

MOSFET Drive

Circuitry with

Break-Before-

Make

SW

L

+

PGND

CGND

SHDN

DC-DC

Controller

PWM

SYNC

Power Up Sequence: The

is recommended to ensure

a safe turn on

Power Down Sequence:

The sequence should be

reverse of the on sequence,

PGND

HS

LS

Figure 7

The SiC714CD10 has a built-in delay time that is optimized for the

MOSFET pair. When the PWM signal goes low, the high-side

on.

the body diode starts to conduct, the high-side MOSFET turns on