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SIP11204DLP-T1-E3 Datasheet(PDF) 9 Page - Vishay Siliconix

Part # SIP11204DLP-T1-E3
Description  Synchronous Rectifier Driver with Power Up/Down Control, Output OVP, Error Amplifier and Precision Reference
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Manufacturer  VISHAY [Vishay Siliconix]
Direct Link  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

SIP11204DLP-T1-E3 Datasheet(HTML) 9 Page - Vishay Siliconix

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Document Number: 73868
S11-0975–Rev. C, 16-May-11
www.vishay.com
9
Vishay Siliconix
SiP11203, SiP11204
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
• While VL is below the UVLOR threshold, the IC
“swaps” the synchronous rectifier drive paths. This
causes the high-going signal on INB to be applied
to the gate of an n-channel hold-off MOSFET,
which is in parallel with the main OUTA driver. This
MOSFET inverts the signal from INB, which causes
its drain to be pulled towards ground. This holds
OUTA low.
• During the deadtime in which neither INB nor INA is
driven high, the voltage on INA and that on INB will
be equal to the voltage on VIN. Depending upon the
exact value of VIN, this may or may not result in
both OUTA and OUTB being pulled low by their
associated inverter MOSFETs.
• During the next cycle of converter operation, all of
the above applies with the exception that INB is
now driven low, which will cause INA to be driven
high. This will in turn cause the hold-off MOSFET in
parallel with the main OUTB driver to conduct,
thereby holding OUTB low.
In this way, the SiP11203/SiP11204 “swap and invert”
function prevents any unwanted turn-on of the
synchronous rectifiers during start-up. Once VL
reaches 90 % of its final value, the drive path inside the
IC is no longer swapped, and the inverting hold-off
MOSFETs are disabled.
FUNCTIONAL BLOCK DIAGRAM
START-UP DRIVER OPERATION
Assuming that VIN rises with suitable rapidity to a
voltage greater than 5.5 V, the factors controlling the
rate of rise of VL are the external VL bypass capacitor
value and the pre-regulator’s current limit. This gives
the following two equations:
• The time from start-up to
CUVLOR  (4.45 V/35 mA) x CVL, and
• The time from start-up to
UVLOR (4.45 V/35 mA) x CVL.
Once VL has reached 90 % of its final value, the clamp
holding VREF at 0 V is released, allowing the voltage on
the VREF pin to rise at a rate set by the value of the
VREF capacitor. This gives the following equation:
• The time from UVLOR to VREF attaining a voltage of
1.1 V
(1.1 V/410 µA) x C
VREF.
These relationships are shown in Figure 4.
Figure 3. During converter startup, the synchronous MOSFET gate-driver outputs of the SiP11203/SiP11204 are reversed and inverted
to prevent spurious MOSFET switching
Hold-off
MOSFET
Hold-off
MOSFET
SW1 and SW2 are closed at start-up.
SW1 and SW2 open when VL > UVLO R.
SW1
SW2


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