ISL70001SEH

11

FN7956.0

November 30, 2011

source. As the soft-start capacitor is charged, the output voltage

slowly ramps to the set point determined by the reference

voltage and the feedback network. Once the voltage on the SS

pin is equal to the internal reference voltage, the soft-start

interval is complete. The controlled ramp of the output voltage

reduces the inrush current during start-up. The soft-start output

ramp interval is defined in Equation 6 and is adjustable from

approximately 2ms to 200ms. The value of the soft-start

peak inrush current can be computed from Equation 7. The soft-

start interval should be long enough to ensure that the peak

inrush current plus the peak output load current does not exceed

the overcurrent trip level of the regulator.

The soft-start capacitor is immediately discharged by a 2.2

Ω

resistor whenever POR conditions are not met or EN is pulled low.

The soft-start discharge time is equal to 256 clock cycles.

Power-Good

The power-good (PGOOD) pin is an open-drain logic output that

indicates when the output voltage of the regulator is within

regulation limits. The power-good pin pulls low during shutdown

and remains low when the controller is enabled. After a

successful soft-start, the PGOOD pin releases, and the voltage

rises with an external pull-up resistor. The power-good signal

transitions low immediately when the EN pin is pulled low.

The power-good circuitry monitors the FB pin and compares it to

the rising and falling thresholds shown in the “Electrical

Specifications” table on page 8. If the feedback voltage exceeds

the typical rising limit of 111% of the reference voltage, the

PGOOD pin pulls low. The PGOOD pin continues to pull low until

the feedback voltage falls to a typical of 107.5% of the reference

voltage. If the feedback voltage drops below a typical of 89% of

the reference voltage, the PGOOD pin pulls low. The PGOOD pin

continues to pull low until the feedback voltage rises to a typical

92.5% of the reference voltage. The PGOOD pin then releases

and signals the return of the output voltage to within the

power-good window.

The PGOOD pin can be pulled up to any voltage from 0V to 5.5V,

independently from the supply voltage. The pull-up resistor

should have a nominal value from 1k

Ω to 10kΩ. The PGOOD pin

should be bypassed to DGND, with a 10nF ceramic capacitor to

mitigate SEE.

Fault Monitoring and Protection

The ISL70001SEH actively monitors output voltage and current

to detect fault conditions. Fault conditions trigger protective

measures to prevent damage to the regulator and external load

device.

Undervoltage Protection

A hysteretic comparator monitors the FB pin of the regulator. The

feedback voltage is compared to an undervoltage threshold that

is a fixed percentage of the reference voltage. Once the

comparator trips, indicating a valid undervoltage condition, a

3-bit undervoltage counter increments. The counter is reset if the

feedback voltage rises back above the undervoltage threshold,

plus a specified amount of hysteresis outlined in the “Electrical

Specifications” table on page 8. If the 3-bit counter overflows, the

undervoltage protection logic shuts down the regulator.

After the regulator shuts down, it enters a delay interval

equivalent to the soft-start interval, which allows the device to

cool. The undervoltage counter is reset when the device enters

the delay interval. The protection logic initiates a normal

soft-start once the delay interval ends. If the output successfully

soft-starts, the power-good signal goes high, and normal

operation continues. If undervoltage conditions continue to exist

during the soft-start interval, the undervoltage counter must

overflow before the regulator shuts down again. This hiccup

mode continues indefinitely until the output soft-starts

successfully.

Overcurrent Protection

A pilot device integrated into the PMOS transistor of Power Block 4

samples current each cycle. This current feedback is scaled and

compared to an overcurrent threshold based on the number of

power blocks connected. Each additional power block connected

beyond Power Block 4 increases the overcurrent limit by 2A. For

example, if three power blocks are connected, the typical current

limit threshold would be 3 x 2A = 6A.

If the sampled current exceeds the overcurrent threshold, a 3-bit

overcurrent counter increments by one LSB. If the sampled current

falls below the threshold before the counter overflows, the counter

is reset. Once the overcurrent counter reaches 111, the regulator

shuts down.

After the regulator shuts down, it enters a delay interval,

equivalent to the soft-start interval, which allows the device to

cool. The overcurrent counter is reset when the device enters the

delay interval. The protection logic initiates a normal soft-start

once the delay interval ends. If the output successfully

soft-starts, the power-good signal goes high, and normal

operation continues. If overcurrent conditions continue to exist

during the soft-start interval, the overcurrent counter must

overflow before the regulator shut downs the output again. This

hiccup mode continues indefinitely until the output soft-starts

successfully.

Note: To prevent severe negative ringing that can disturb the

overcurrent counter, it is recommended that a Schottky diode of

appropriate rating be added from the LXx pins to the PGNDx pins.

Feedback Loop Compensation

To reduce the number of external components and to simplify the

process of determining compensation components, the

ISL70001SEH PWM controller has an internally compensated

error amplifier.

Due to the current loop feedback in peak current mode control, the

modulator has a single pole response with -20dB slope at a

frequency determined by the load (Equation 8):

-------------

⋅

=

(EQ. 6)

-------------

⋅

=

(EQ. 7)

1

2

⋅⋅

-------------------------------------

=

(EQ. 8)