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XO-52AARE40ME2 Datasheet(PDF) 1 Page - Vishay Siliconix |
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XO-52AARE40ME2 Datasheet(HTML) 1 Page - Vishay Siliconix |
1 / 3 page Document Number: 35025 For technical questions, contact: frequency@vishay.com www.vishay.com Revision: 08-Mar-11 27 Half Size Clock Oscillator Enable/Disable XO-52 Vishay Dale The XO-52 series oscillator is half size, has tri-state enable/disable controlled function. The metal package with pin 4 case ground acts as shielding to minimize EMI radiation. FEATURES • Size: 8 pin half size • Industry standard • Tri-state enable/disable • Wide frequency range •Low cost • Resistance weld package •5 V • Compliant to RoHS Directive 2002/95/EC • Halogen-free according to IEC 61249-2-21 definition Note (1) Include: 25 °C tolerance, operating temperature range, input voltage change, aging, load change, shock vibration STANDARD ELECTRICAL SPECIFICATIONS PARAMETER SYMBOL CONDITION VALUE Frequency range FO - 1.000 MHz to 100.000 MHz Frequency stability (1) all conditions ± 25 ppm, ± 50 ppm, ± 100 ppm Operating temperature range TOPR - 0 ºC to 70 ºC - 40 ºC to + 85 ºC (option) Storage temperature range TSTG - - 55 ºC to + 125 ºC Power supply voltage VDD - 5.0 V ± 10 % Aging (first year) 25 ºC ± 3 ºC ± 5 ppm Supply current IDD 1.000 MHz to 23.999 MHz 20 mA max. 24.000 MHz to 49.999 MHz 30 mA max. 50.000 MHz to 69.999 MHz 40 mA max. 70.000 MHz to 100.000 MHz 60 mA max. Output symmetry Sym at 1/2 VDD 40 %/60 % (45 %/55 % option) Rise time tr 20 % VDD to 80 % VDD 10 ns max. Fall time tf 80 % VDD to 20 % VDD 10 ns max. Output voltage VOH - 90 % VDD min. VOL - 10 % VDD max. Output load TTL load - 1 TTL to 10 TTL HCMOS load - to 50M: 50 pF - to 70M: 30 pF - to 100M: 15 pF Start-up time ts -10 ms max. Pin 1, tri-state function - pin 1 = H or open (output active at pin 5) pin 1 = L (high impedance at pin 5) DIMENSIONS in inches [millimeters] MARKING AREA HCMOS TEST CIRCUIT 0.220 [5.6] max. [0.45 ± 0.1] [0.8 ± 0.1] 0.268 [6.80] max. HCMOS OUTPUT WAVEFORM 0.031 ± 0.003 0.018 ± 0.003 VOH VOL Tr Tf 90 % VDD 50 % VDD 10 % VDD GND T1 T0 = 1/Fo SYMMETRY = x 100 % T1 T0 + 5.0 V Test Point CL (1) 0.01 µF CMOS Load Note (1) Includes Stray and Probe Capacitance INH + 3.3 V Enable/Disable function ENABLE/DISABLE FUNCTION INPUT (PIN 1) OPEN VIH ≥ 2.2 VDC OUTPUT (PIN 5) ENABLE ENABLE PIN #1 #4 #5 #8 CONNECTION N.C. GND OUTPUT VDD #1 #4 #5 #8 0.508 [12.9] max. 0.300 ± 0.005 [7.62 ± 0.13] 0.580 [12.9] max. 0.300 ± 0.005 [7.62 ± 0.13] A V #8 #1 #5 #4 CL = 15 pF or 50 pF spec. sheet) (see individual |
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