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W29GL064CL7B Datasheet(PDF) 4 Page - Winbond

Part # W29GL064CL7B
Description  64M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE
Download  66 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W29GL064CL7B Datasheet(HTML) 4 Page - Winbond

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W29GL064C
ii
7.6
Common Flash Memory Interface (CFI) Mode ............................................................. 25
7.6.1 Query Instruction and Common Flash memory Interface (CFI) Mode.............................25
8
ELECTRICAL CHARACTERISTICS......................................................................................... 29
8.1
Absolute Maximum Stress Ratings............................................................................... 29
8.2
Operating Temperature and Voltage ............................................................................ 29
8.3
DC Characteristics ........................................................................................................ 30
8.4
Switching Test Circuits.................................................................................................. 31
8.4.1 Switching Test Waveform ...............................................................................................31
8.5
AC Characteristics ........................................................................................................ 32
8.5.1 Instruction Write Operation .............................................................................................33
8.5.2 Read / Reset Operation ..................................................................................................34
8.5.3 Erase/Program Operation ...............................................................................................36
8.5.4 Write Operation Status....................................................................................................45
8.5.5 WORD/BYTE CONFIGURATION (#BYTE).....................................................................49
8.5.6 DEEP POWER DOWN MODE........................................................................................51
8.5.7 WRITE BUFFER PROGRAM..........................................................................................51
8.6
Recommended Operating Conditions........................................................................... 52
8.6.1 At Device Power-up ........................................................................................................52
8.7
Erase and Programming Performance ......................................................................... 53
8.8
Data Retention .............................................................................................................. 53
8.9
Latch-up Characteristics ............................................................................................... 53
8.10
Pin Capacitance............................................................................................................ 53
9
PACKAGE DIMENSIONS ......................................................................................................... 54
9.1
TSOP 48-pin 12x20mm ................................................................................................ 54
9.2
TSOP 56-pin 14x20mm ................................................................................................ 55
9.3
Low-Profile Fine-Pitch Ball Grid Array, 64-ball 11x13mm (LFBGA64) ......................... 56
9.4
Thin & Fine-Pitch Ball Grid Array, 6x8 mm2, ball pitch: 0.8 mm, ∅=0.4mm (TFBGA48)
57
10
ORDERING INFORMATION..................................................................................................... 58
10.1
Ordering Part Number Definitions................................................................................. 58
10.2
Valid Part Numbers and Top Side Marking .................................................................. 59
11
HISTORY .................................................................................................................................. 60
List of Figures
Figure 3-1
LFBGA64 TOP VIEW (FACE DOWN)........................................................................... 2
Figure 3-2
56-PIN STANDARD TSOP (TOP VIEW)........................................................................ 2
Figure 3-3
TFBGA48 TOP VIEW (FACE DOWN)............................................................................ 2
Figure 3-4
48-PIN STANDARD TSOP (TOP VIEW)........................................................................ 2
Figure 4-1
Block Diagram................................................................................................................. 3
Figure 7-1
Enhanced Sector Protect/Un-protect IPB Program Algorithm...................................... 15
Figure 7-2
Lock Register Program Algorithm................................................................................. 16
Figure 7-3
IPB Program Algorithm ................................................................................................. 18
Figure 8-1
Maximum Negative Overshoot ..................................................................................... 29
Figure 8-2
Maximum Positive Overshoot ....................................................................................... 29
Figure 8-3
Switch Test Circuit ........................................................................................................ 31
Figure 8-4
Switching Test Waveform ............................................................................................. 31


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