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W947D2HBJX6E Datasheet(PDF) 6 Page - Winbond |
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W947D2HBJX6E Datasheet(HTML) 6 Page - Winbond |
6 / 60 page W947D6HB / W947D2HB 128Mb Mobile LPDDR Publication Release Date:Jun,17, 2011 - 6 - Revision A01-003 4. PIN DESCRIPTION 4.1 Signal Descriptions SIGNAL NAME TYPE FUNCTION DESCRIPTION A [n : 0] Input Address Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. The address inputs also provide the opcode during a MODE REGISTER SET command. A10 is used for Auto Pre-charge Select. BA0, BA1 Input Bank Select Define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. DQ0~DQ15 (×16) DQ0~DQ31 (×32) I/O Data Input/ Output Data bus: Input / Output. CS Input Chip Select CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS Input Row Address Strobe RAS , CAS and WE (along with CS ) define the command being entered. CAS Input Column Address Strobe Referred to RAS WE Input Write Enable Referred to RAS UDM / LDM(x16); DM0 to DM3 (x32) Input Input Mask Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading. x16: LDM: DQ0 - DQ7, UDM: DQ8 – DQ15 x32: DM0: DQ0 - DQ7, DM1: DQ8 – DQ15, DM2: DQ16 – DQ23, DM3: DQ24 – DQ31 CK / CK Input Clock Inputs CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK .Input and output data is referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are derived from CK/ CK . |
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