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W948D6FBHX6G Datasheet(PDF) 7 Page - Winbond |
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W948D6FBHX6G Datasheet(HTML) 7 Page - Winbond |
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7 / 60 page  W948D6FB / W948D2FB 256Mb Mobile LPDDR Publication Release Date : May, 24, 2011 - 7 - Revision A01-003 SIGNAL NAME TYPE FUNCTION DESCRIPTION CKE Input Clock Enable CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE, POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE, are disabled during power down and self refresh mode which are contrived for low standby power consumption. LDQS, UDQS (x16); DQS0~DQS3 (x32) I/O Data Strobe Output with read data, input with write data. Edge-aligned with read data, centered with write data. Used to capture write data. x16: LDQS: DQ0~DQ7; UDQS: DQ8~DQ15. x32: DQS0: DQ0~DQ7; DQS1: DQ8~DQ15; DQS2: DQ16~DQ23; DQS3: DQ24~DQ31. VDD Supply Power Power supply for input buffers and internal circuit. VSS Supply Ground Ground for input buffers and internal circuit. VDDQ Supply Power for I/O Buffer Power supply separated from VDD, used for output drivers to improve noise. VSSQ Supply Ground for I/O Buffer Ground for output drivers. NC - No Connect No internal electrical connection is present. 4.2 Addressing Table ITEM 256 Mb Number of banks 4 Bank address pins BA0,BA1 Auto precharge pin A10/AP X16 Row addresses A0-A12 Column addresses A0-A8 tREFI(µs) 7.8 x32 Row addresses A0-A11 Column addresses A0-A8 tREFI(µs) 15.6 |
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