Part Name
         Description
W9425G8EH

 8M × 4 BANKS × 8 BITS DDR SDRAM ( 53 Page)


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W9425G8EH
Publication Release Date: Jul. 04, 2008
- 49 -
Revision A01
11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)
CMD
DQS
CLK
CLK
DQ
Q0a
Q1a
Q0b
Q1b
ACTa/b/c/d
: Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CM D of bank a/b/c/d
APa/b/c/d
: Auto Pre. of bank a/b/c/d
ACTa
ACTb
READAa
ACTc
READAb
ACTd
READAc
ACTa
APa
APb
tRCD(a)
tRAS(a)
tRP
tRAS(b)
tRCD(b)
CL(a)
CL(b)
Pream ble
Postam ble Preamble
tRRD
tRC(a)
tRRD
tRAS(c)
tRAS(d)
tRCD(d)
tRCD(c)
tRRD
tRRD
11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)
CM D
DQ S
CL K
CL K
DQ
A C T a/b/c /d
: B ank A c t. C M D of bank a /b/c /d
R E A D A a/b/c /d : R ead w ith A uto P re.C M D of bank a/b/c /d
A P a/b/c /d
: A uto P re. of bank a /b/c /d
AC T a
R EAD Aa
AC T b
R E AD Ab
AC T c
R EAD Ac
AC T d
R EAD Ad
AC T a
APa
APb
tRCD(a)
tRA S (a)
tRP (a)
tRA S (b)
tRCD(b)
C L(a)
C L(b)
tRRD
tRC(a)
tRR D
tR AS(c)
tRA S (d)
tRCD (d)
tRCD (c)
tRRD
tRRD
Q2 a
Q3 a
Q2 b
Q3 b
P ream ble
Q0 a
Q1 a
Q0 b
Q1 b
Q0 a
Q1 a
CL (c )
APc



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