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ATXMEGA128D4_1012 Datasheet(PDF) 6 Page - ATMEL Corporation |
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ATXMEGA128D4_1012 Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 105 page  6 8135J–AVR–12/10 XMEGA D4 3.1 Block Diagram Figure 3-1. XMEGA D4 Block Diagram Power Supervision POR/BOD & RESET PORT A (8) PORT B (8) BUS Controller SRAM ADCA ACA OCD PDI CPU A[0..7] B[0..7] Interrupt Controller DATA BUS Prog/Debug Controller VCC GND Oscillator Control Event System Controller PDI_DATA RESET/ PDI_CLK Sleep Controller Flash EEPROM NVM Controller IRCOM PORT C (8) PC[0..7] PD[0..7] PORT D (8) Int. Refs. AREFA AREFB Tempref VCC/10 EVENT ROUTING NETW ORK DATA BUS W atchdog Timer Watchdog Oscillator Oscillator Circuits/ Clock Generation Real Time Counter PORT R (2) XTAL1/ TOSC1 XTAL2/ TOSC2 PR[0..1] PE[0..3] PORT E (4) |
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