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UCC27523 Datasheet(PDF) 5 Page - Texas Instruments |
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UCC27523 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 31 page  UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3B – NOVEMBER 2011 – REVISED DECEMBER 2011 ELECTRICAL CHARACTERISTICS VDD = 12 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal (unless otherwise noted,) PARAMETER TEST CONDITION MIN TYP MAX UNITS Bias Currents VDD = 3.4 V, INA=VDD, 55 110 175 Startup current, INB=VDD IDD(off) (based on UCC27524 Input μA VDD = 3.4 V, configuration) INA=GND, 25 75 145 INB=GND Under Voltage LockOut (UVLO) TJ = 25°C 3.91 4.20 4.50 VON Supply start threshold TJ = -40°C to 140°C 3.70 4.20 4.65 V Minimum operating voltage VOFF 3.40 3.90 4.40 after supply start VDD_H Supply voltage hysteresis 0.20 0.30 0.50 Inputs (INA, INB, INA+, INA-, INB+, INB-) Output High for Non-inverting input pins VIN_H Input signal high threshold 1.9 2.1 2.3 Output Low for Inverting input pins Output Low for Non-inverting input pins V VIN_L Input signal low threshold 1.0 1.2 1.4 Output High for Inverting input pins VIN_HYS Input hysteresis 0.70 0.90 1.10 Enable (ENA, ENB) (UCC27523, UCC27524, UCC27525) VEN_H Enable signal high threshold Output enabled 1.9 2.1 2.3 VEN_L Enable signal low threshold Output disabled 0.95 1.15 1.35 V VEN_HYS Enable hysteresis 0.70 0.95 1.10 Outputs (OUTA, OUTB) ISNK/SRC Sink/source peak current(1) CLOAD = 0.22 µF, FSW = 1 kHz ±5 A VDD-VOH High output voltage IOUT = -10 mA 0.075 V VOL Low output voltage IOUT = 10 mA 0.01 ROH Output pull-up resistance IOUT = -10 mA 2.5 5 7.5 Ω ROL Output pull-down resistance IOUT = 10 mA 0.15 0.5 1 Ω Switching Time tR Rise time (2) CLOAD = 1.8 nF 7 18 tF Fall time(2) CLOAD = 1.8 nF 6 10 Delay matching between 2 INA = INB, OUTA and OUTB at 50% transition tM 1 4 channels point Minimum input pulse width ns tPW 10 20 that changes the output state Input to output propagation tD1, tD2 CLOAD = 1.8 nF, 5-V input pulse 6 13 23 delay (2) EN to output propagation tD3, tD4 CLOAD = 1.8 nF, 5-V enable pulse 6 13 23 delay (2) (1) Ensured by design. (2) See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4 Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): UCC27523, UCC27524, UCC27525, UCC27526 |
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