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XR16M890 Datasheet(PDF) 6 Page - Exar Corporation |
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XR16M890 Datasheet(HTML) 6 Page - Exar Corporation |
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6 / 63 page  XR16M890 6 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS REV. 1.0.0 INT (IRQ#) 10 12 15 O (OD) When 16/68# pin is at logic 1 for Intel bus interface, this output become the active high device interrupt output. The output state is defined by the user through the software setting of MCR[3]. INT is set to the active mode when MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes the active low device interrupt output (open drain). An external pull-up resistor is required for proper operation. RESET (RESET#) 9 10 13 I When 16/68# pin is at logic 1 for Intel bus interface, this input becomes RESET (active high). When 16/68# pin is at logic 0 for Motorola bus interface, this input becomes RESET# (active low). A 40 ns minimum active pulse on this pin will reset the internal reg- isters and all outputs of the UART. The UART transmitter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period (see UART Reset Conditions). DATA BUS INTERFACE - VLIO VLIO_EN 28 37 45 I VLIO Bus Enable. When VLIO_EN pin is at logic 0, the bus interface is selected by the 16/68# pin. When VLIO_EN pin is at logic 1, the VLIO bus interface is enabled and the 16/68# pin has no effect. AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 I/O Multiplexed Address/Data lines [7:0]. The register address is latched on the rising edge of the LLA#. After the LLA# signal goes high, the UART enters the data phase where the data is placed on these lines. IOR# 13 16 10 I Read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the latched address. The UART places the data byte on the data bus to allow the host processor to read it on the rising edge. IOW# 14 17 11 I Write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the latched address. CS# 15 18 12 I Chip select (active low). The falling edge starts the access to the UART. A read or write is determined by the IOR# and IOW# sig- nals. LLA# 31 40 48 I Latch Lower Address (active low). The register address is latched on the rising edge of the LLA# signal. After the LLA# goes high, the device enters the data phase where the data is placed on the AD[7:0] lines. In the Intel/Motorola mode, this pin becomes A0. Pin Description NAME QFN-32 PIN# QFN-40 PIN# TQFP-48 PIN# TYPE DESCRIPTION |
Similar Part No. - XR16M890_11 |
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Similar Description - XR16M890_11 |
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