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9DB102BGILFT Datasheet(PDF) 1 Page - Integrated Device Technology |
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9DB102BGILFT Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 13 page ICS9DB102 IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV K 04/01/10 Two Output Differential Buffer for PCIe Gen1 & Gen2 DATASHEET 1 SPREAD COMPATIBLE PLL CONTROL LOGIC SMBDAT SMBCLK CLK_INT C LK_IN C PLL_BW IREF PCIEX0 PCIEX1 CLKREQ1# CLKREQ0# Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. • 2 - 0.7V current mode differential output pairs (HCSL) Functional Block Diagram Key Specifications • Cycle-to-cycle jitter < 35ps • Output-to-output skew < 25ps Features/Benefits • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused outputs can be disabled • Industrial temperature range available |
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