Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

1371F — 09/23/09

ICS9FG1201H

Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

6

Byte 8,

bit 2

FSC

Byte 8,

bit 1

FSB

Byte 8,

bit 0

FS_A_410

CLK_IN

(CPU FSB)

MHz

1:1 DIF

Outputs

MHz

Notes

1

0

1

100.00

100.00

3

0

0

1

133.33

133.33

3

0

1

1

166.67

166.67

1

0

1

0

200.00

200.00

3

0

0

0

266.67

266.67

3

1

0

0

333.33

333.33

3

1

1

0

400.00

400.00

2

1

1

1

Notes:FS_A_410 = 1

1. Powerup Default for FS_A_410 = 1

2. Powerup Default for FS_A_410 = 0

3. Setting the exact FSB frequency after Power up is required for best phase noise performance.

Reserved

ICS 9FG1201H 1:1 PLL Programming