IDT5P49EE601

EEPROM CLOCK GENERATOR

4

IDT5P49EE601 REV C 061110

Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL. Differential LVDS interface

levels can be generated for OUT4A/OUT4B when connected to VDDO1=3.3V and registers configured

appropriately. Alway completely power up VDD and VDDx prior to applying VDDO power.

Note 2: Default configuration CLK1=Buffered MHz Reference output and CLK2=Buffered 32.768kHz output. All

other outputs are off.

GND

13

Power

Connect to Ground.

VDD

14

Power

Device power supply. Connect to 1.8V.

OUT0

15

O

Adjustable

Configurable clock output 0. Single-ended output voltage levels

are register controlled by either VDDO1, VDDO2 or VDDO3.

VDDO3

16

Power

Device power supply. Connect to 1.8 to 3.3V. Using register

settings, select output voltage levels for OUT0-OUT4. VDDO3

must be equal or less than VDDO1.

SCLK

17

I

LVTTL

OUT4B

18

O

Adjustable

Configurable clock output 4B. Single-ended or differential when

combined with OUT4A. Output voltage levels are controlled by

VDDO1.

OUT4A

19

O

Adjustable

Configurable clock output 4A. Single-ended or differential when

combined with OUT4B. Output voltage levels are controlled by

VDDO1.

SDA

20

I/O

Open Drain

VDD

21

Power

Device power supply. Connect to 1.8V.

GND

22

Power

Connect to Ground.

XIN/ REF

23

I

LVTTL

MHz CRYSTAL_IN -- Reference crystal input or external

reference clock input.

XOUT

24

O

LVTTL

MHz CRYSTAL_OUT -- Reference crystal feedback.