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COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT23S05T

2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE

MAY 2010

2006

Integrated Device Technology, Inc.

DSC 6397/11

c

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five outputs

• Zero Input-Output Delay

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• No external RC network required

• Power down mode

• Spread spectrum compatible

• Available in SOIC package

FUNCTIONAL BLOCK DIAGRAM

IDT23S05T

2.5V ZERO DELAY CLOCK

BUFFER, SPREAD SPECTRUM

COMPATIBLE

PLL

8

CLK1

CLK2

CLK3

CLK4

Control

Logic

REF

CLKOUT

1

3

2

5

7

DESCRIPTION:

The IDT23S05T is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

The IDT23S05T is an 8-pin version of the IDT23S09T. IDT23S05T

accepts one reference input, and drives out five low skew clocks. All parts

have on-chip PLLs which lock to an input clock on the REF pin. The PLL

feedback is on-chip and is obtained from the CLKOUT pad. In the absence

of an input clock, the IDT23S05T enters power down. In this mode, the

device will draw less than 12

µA for Commercial Temperature Range and

and less than 25

µA for Industrial temperature range, the outputs are tri-

stated, and the PLL is not running, resulting in a significant reduction of

power. The IDT23S05T is characterized for both Industrial and Commer-

cial operation.