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ACS422A67TAGYYX Datasheet(PDF) 11 Page - Integrated Device Technology

Part # ACS422A67TAGYYX
Description  PORTABLE CONSUMER CODEC
Download  87 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ACS422A67TAGYYX Datasheet(HTML) 11 Page - Integrated Device Technology

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V1.1 01/12
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
ACS422X67
ACS422x67
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
2.2.
Stopping the Master Clock
In order to minimize digital core power consumption, the master clock may be stopped in Standby and OFF modes by
setting the DIGENB bit (R25, bit 0).
Note: Before DIGENB can be set, the control bits ADCL, ADCR, HPL, HPR, SPKL, and SPKR
must be set to zero and a waiting time of 100ms must be observed to allow port ramping/gain
fading to complete. Any failure to follow this procedure may cause pops or, if less than 1mS, may
prevent the DACs and ADCs from re-starting correctly.
Register Address
Bit
Label
Type
Default
Description
0x1A
Power Management 1
0DIGENB
RW
0
Master clock disable
0 = master clock enabled, 1 = master clock disabled
Table 3. Power Management Register1 -- Master Clock Disable


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