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ACS422D67TAGYYX Datasheet(PDF) 8 Page - Integrated Device Technology |
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ACS422D67TAGYYX Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 87 page  8 V1.1 01/12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422X67 ACS422x67 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 1. OVERVIEW 1.1. Block Diagrams The ACS422x67 is an advanced low power codec with integrated amplifiers and timing generators. To support the design of audio subsystems in a portable device, the ACS422x67 features an intelligent codec architecture with advanced audio processing algorithms, integrated with a true cap-less headphone amplifier, 1W/channel (8 ) or 2W/channel (4 ) filterless DDXTM stereo class D amplifier, and microphone interface with programmable gain. Figure 1. Block Diagram 1.2. Audio Outputs The ACS422x67 provides multiple outputs for analog sound. Audio outputs include: • A 1W/channel (8 ) or 2W/channel (4) filterless DDXTM Class D amplifier. This amplifier is capable of driving the speakers typically found in portable equipment, providing high fidelity, high efficiency, and excellent sound quality. •A line-out/capless stereo headphone port with ground referenced outputs, capable of driving headphones without requiring an external DC blocking capacitor. Each endpoint features independent volume controls, including a soft-mute capability which can slowly ramp up or down the volume changes to avoid unwanted audio artifacts. The ACS422x67 output signal paths consist of digital filters, DACs and output drivers. The digital filters and DACs are enabled when the ACS422x67 is in ‘playback only’ or ‘record and playback’ mode. The output drivers can be sepa- rately enabled by individual control bits. PLL Audio Processing Bass/Treble Enhancement SYSTEM EQ SPEAKER EQ 3-D effect Compressor-limiter Dynamic Range Expander Audio Processing DAC Left HP Out Left HP SPKR + BTL Digital PWM controller LIN3/DMIC_CLK* RIN1 DACIN VOL mute ADCOUT Anti- pop DAC Left HP Out Right HP Anti- pop DAC Right Audio Processing VOL mute MIC Bias LIN1 LIN2 D2S + - RIN2 RIN3/DMIC_DAT* LIN1 LIN2 RIN1 RIN2 RIN1 RIN2 RIN3 D2S LIN1 LIN2 LIN3 D2S D2S S Clocking Control I2C_SCL I2C_SDA DACLRCLK ADCLRCLK DACBCLK ADCBCLK MCLK/XTAL_IN Internal Audio Clock(s) PVDD DVDD_CORE CPVDD Vref AGND + - DVDD_IO Charge-Pump AVDD CAP+ CAP- V- DAC Right DAC DAC ADCL ADCR -97 to +30 dB In 0.5 dB steps -97 to +30 dB In 0.5 dB steps vol Digital Volume Digital Volume Automatic Level Control 4 2 DVSS AVSS CPGND PVSS 3 4 Vref AFILT1 AFILT2 HP_DET TEST 3 VDD_XTAL VDD_PLL2 VDD_PLL1 VDD_PLSS VSS_PLSS VSS_XTAL +0/+10/+20/+30 dB Boost AGC -17 to +30dB in 0.75dB steps +0/+10/+20/+30 dB Boost -17 to +30dB in 0.75dB steps AGC 2 SPKR - VDD_PLL3 *Digital Microphone Products XTAL_OUT REF_OUT |
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