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ACS42200 Datasheet(PDF) 5 Page - Integrated Device Technology |
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ACS42200 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 89 page  5 V0.8 04/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422X00 ACS422x00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC LIST OF FIGURES Figure 1. Block Diagram ...................................................................................................................................8 Figure 2. Output Audio Processing ................................................................................................................12 Figure 3. Prescaler & EQ Filters ....................................................................................................................15 Figure 4. 6-Tap IIR Equalizer Filter ................................................................................................................15 Figure 5. DAC Coefficient RAM Write Sequence ...........................................................................................17 Figure 6. DAC Coefficient RAM Read Sequence ...........................................................................................18 Figure 7. Gain Compressor, Output vs Input .................................................................................................21 Figure 8. Compressor block diagram .............................................................................................................23 Figure 9. 3-D Channel Inversion ....................................................................................................................29 Figure 10. Bass Enhancement .......................................................................................................................29 Figure 11. Treble Enhancement ....................................................................................................................30 Figure 12. Interpolation and Filtering .............................................................................................................32 Figure 13. Constant Output Power Error ........................................................................................................36 Figure 14. Constant Output Power nominal and high/low ..............................................................................36 Figure 15. Temp sense volume adjustment algorithm ...................................................................................43 Figure 16. Input Audio Processing .................................................................................................................47 Figure 17. Mic Bias ........................................................................................................................................50 Figure 18. ADC Filter Data path .....................................................................................................................51 Figure 19. ADC Input processing ...................................................................................................................52 Figure 20. ALC Operation ..............................................................................................................................54 Figure 21. Single Digital Microphone (data is ported to both left and right channels) ....................................59 Figure 22. Stereo Digital Microphone Configuration ......................................................................................60 Figure 23. Master mode .................................................................................................................................61 Figure 24. Slave mode ...................................................................................................................................61 Figure 25. Left Justified Audio Interface (assuming n-bit word length) ..........................................................62 Figure 26. Right Justified Audio Interface (assuming n-bit word length) ........................................................62 Figure 27. I2S Justified Audio Interface (assuming n-bit word length) ...........................................................63 Figure 28. Bit Clock mode ..............................................................................................................................67 Figure 29. 2-Wire Serial Control Interface ......................................................................................................68 Figure 30. Multiple Write Cycle ......................................................................................................................68 Figure 31. Read Cycle ...................................................................................................................................69 Figure 32. Multiple Read Cycle ......................................................................................................................69 Figure 33. PLL Block Diagram .......................................................................................................................74 Figure 34. ACS422A00 Pinout .......................................................................................................................82 Figure 35. ACS422D00 Pinout .......................................................................................................................83 Figure 36. Package Outline ...........................................................................................................................87 |
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