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841N254AKIT Datasheet(PDF) 1 Page - Integrated Device Technology |
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841N254AKIT Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  DATA SHEET ICS841N254AKI REVISION A APRIL 18, 2011 1 ©2011 Integrated Device Technology, Inc. FEMTOCLOCK® NG Crystal-to-LVDS/HCSL Clock Synthesizer ICS841N254I General Description The ICS841N254I is a 4-output clock synthesizer designed for S-RIO 1.3 and 2.0 reference clock applications. The device generates four copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz clock signal with excellent phase jitter performance. The four outputs are organized in two banks of two LVDS and two HCSL ouputs.The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. The synthesized clock frequency and the phase-noise performance are optimized for driving RIO 1.3 and 2.0 SerDes reference clocks. The device supports 3.3V and 2.5V voltage supplies and is packaged in a small 32-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. Features • Fourth generation FemtoClock® (NG) technology • Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output clock synthesized from a 25MHz fundamental mode crystal • Four differential clock outputs (two LVDS and two HCSL outputs) • Crystal interface designed for 25MHz, parallel resonant crystal • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1MHz - 20MHz): 0.27ps (typical) • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz - 20MHz): 0.32ps (typical) • Power supply noise rejection PSNR: -50dB (typical) • LVCMOS interface levels for the frequency select input • Full 3.3V or 2.5V supply voltage • Available in both standard (RoHS 5) and Lead-free (RoHS 6) packages • -40°C to 85°C ambient operating temperature Function Table NOTE: F_SEL[1:0] are asynchronous controls. Inputs Output Frequency with fXTAL = 25MHz F_SEL1 F_SEL0 0 (default) 0 (default) 156.25MHz 0 1 125MHz 1 0 100MHz 1 1 250MHz QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 Pulldown Pulldown Pulldown Pulldown Pulldown OSC XTAL_IN XTAL_OUT REF_CLK REF_SEL BYPASS F_SEL[0:1] nOEA nOEB IREF ÷25 ÷N PFD & LPF FemtoClock® NG VCO 625MHz Pulldown LVDS LVDS HCSL HCSL 0 1 1 0 2 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 VDD nc VDDA nc GND REF_CLK nOEA VDD IREF GND nQA0 QA0 VDDOA nQA1 QA1 GND ICS841N254I 32-lead VFQFN K Package 5mm x 5mm x 0.925mm package body Top View Block Diagram Pin Assignment |
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