ICS83905 Data Sheet

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS83905AM REVISION B JULY 20, 2009

6

©2009 Integrated Device Technology, Inc.

AC Electrical Characteristics

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

All parameters measured at ƒ

≤ f

Terminated at 50

NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: See phase noise plot.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

All parameters measured at ƒ

≤ f

Terminated at 50

NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: See phase noise plot.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

Using External Crystal

10

40

MHz

Using External Clock

Source NOTE 1

DC

100

MHz

tsk(o)

Output Skew; NOTE 2, 3

80

ps

tjit(Ø)

RMS Phase Jitter (Random); NOTE 4

25MHz, Integration Range:

100Hz – 1MHz

0.13

ps

Output Rise/Fall Time

20% to 80%

200

800

ps

odc

Output Duty Cycle

48

52

%

Output Enable

Time; NOTE 5

ENABLE1

4

cycles

ENABLE2

4

cycles

Output Disable

Time; NOTE 5

ENABLE1

4

cycles

ENABLE2

4

cycles

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

Using External Crystal

10

40

MHz

Using External Clock

Source NOTE 1

DC

100

MHz

tsk(o)

Output Skew; NOTE 2, 3

80

ps

tjit

RMS Phase Jitter (Random); NOTE 4

25MHz, Integration Range:

100Hz – 1MHz

0.26

ps

Output Rise/Fall Time

20% to 80%

200

800

ps

odc

Output Duty Cycle

47

53

%

Output Enable

Time; NOTE 5

ENABLE1

4

cycles

ENABLE2

4

cycles

Output Disable

Time; NOTE 5

ENABLE1

4

cycles

ENABLE2

4

cycles