ICS843001CGI-23 REVISION A OCTOBER 4, 2011

2

©2011 Integrated Device Technology, Inc.

ICS843001I-23 Data Sheet

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

Power

Output supply pin for REF_CLK output.

2, 3

N0, N1

Input

Pulldown

Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3C.

4

N2

Input

Pullup

Power

Output supply pin for LVPECL output.

6, 7

Q, nQ

Output

Differential output pair. LVPECL interface levels.

8, 23

Power

Negative supply pins.

Power

Analog supply pin.

10

Power

Core supply pin.

11,

12

XTAL_OUT1,

XTAL_IN1

Input

Parallel resonant crystal interface.

XTAL_OUT1 is the output, XTAL_IN1 is the input.

13,

14

XTAL_OUT0,

XTAL_IN0

Input

Parallel resonant crystal interface.

XTAL_OUT0 is the output, XTAL_IN0 is the input.

15

CLK

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

16, 17

SEL0, SEL1

Input

Pulldown

Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D.

18

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true output Q to go low and the inverted output nQ to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS/LVTTL interface levels.

19, 20, 21

M0, M1, M2

Input

Pullup

Feedback divider select pins. LVCMOS/LVTTL interface levels. See Table 3B.

22

OE_REF

Input

Pulldown

Reference clock output enable. Default LOW. See Table 3E.

LVCMOS/LVTTL interface levels.

24

REF_OUT

Output

Reference clock output. LVCMOS/LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4pF

Input Pullup Resistor

51

k

Ω

51

k

Ω

Output Impedance

REF_OUT

21

Ω

25

Ω