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IDT82P20516DBFBLANK Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT82P20516DBFBLANK Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 115 page  8 December 17, 2009 IDT82P20516 2009 Integrated Device Technology, Inc. DSC-7266/- 16-Channel Short Haul E1 Line Inter- face Unit IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. FEATURES Integrates 16 channels E1 short haul line interface units for 120 Ω E1 twisted pair cable and 75 Ω E1 coaxial cable applications Per-channel configurable Line Interface options • Fully integrated and software selectable receive and transmit termination – Option 1: Fully Internal Impedance Matching with integrated receive termination resistor – Option 2: Partially Internal Impedance Matching with common external resistor for improved device power dissipation – Option 3: External impedance Matching termination • Supports global configuration and per-channel configuration to E1 mode Per-channel programmable features • Provides E1 short haul waveform templates and user- programmable arbitrary waveform templates • Provides two JAs (Jitter Attenuator) for each channel of receiver and transmitter • Supports AMI/HDB3 (for E1) encoding and decoding Per-channel System Interface options • Supports Single Rail, Dual Rail with clock or without clock and sliced system interface • Integrated Clock Recovery for the transmit interface to recover transmit clock from system transmit data Per-channel system and diagnostic functions • Provides transmit driver over-current detection and protection with optional automatic high impedance of transmit interface • Detects and generates PRBS (Pseudo Random Bit Sequence), ARB (Arbitrary Pattern) and IB (Inband Loopback) in either receive or transmit direction • Provides defect and alarm detection in both receive and transmit directions. – Defects include BPV (Bipolar Violation) /CV (Code Violation) and EXZ (Excessive Zeroes) – Alarms include LLOS (Line LOS), SLOS (System LOS), TLOS (Transmit LOS) and AIS (Alarm Indication Signal) • Programmable LLOS detection /clear levels. Compliant with ITU and ANSI specifications • Various pattern, defect and alarm reporting options – Serial hardware LLOS reporting (LLOS, LLOS0) for all 16 channels – Register access to individual registers or 16-bit error counters • Supports Analog Loopback, Digital Loopback and Remote Loopback • Supports line monitor Hitless Protection Switching (HPS) without external Relays • Supports 1+1 and 1:1 hitless protection switching • Asynchronous hardware control (OE, RIM) for fast global high impedance of receiver and transmitter (hot switching between working and backup board) • High impedance transmitter and receiver while powered down • Per-channel register control for high impedance, independent for receiver and transmitter Clock Inputs and Outputs • Flexible master clock (N x 1.544 MHz or N x 2.048 MHz) (1 ≤ N ≤ 8, N is an integer number) • Integrated clock synthesizer can multiply or divide the reference clock to a wide range of frequencies: 8 KHz, 64 KHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 19.44 MHz and 32.768 MHz Microprocessor Interface • Supports Serial microprocessor interface Other Key Features • IEEE1149.1 JTAG boundary scan • Two general purpose I/O pins • 3.3 V I/O with 5 V tolerant inputs • 3.3 V and 1.8 V power supply • Package: 484-pin Fine Pitch BGA (19 mm X 19 mm) Applicable Standards • Bellcore TR-TSY-000009, GR-253-CORE and GR-499-CORE • ETSI CTR12/13 • ETS 300166 and ETS 300 233 • G.703, G.735, G.736, G.742, G.772, G.775, G.783 and G.823 • O.161 |
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