MC88915

MOTOROLA

TIMING SOLUTIONS

BR1333 — Rev 6

2

MC88915 Block Diagram

M

U

X

0

1

M

U

X

0

1

MUX

1

0

PLL_EN

R

R

R

R

R

R

R

RST

FEEDBACK

Q/2

Q

CP

D

LOCK

Q5

Q4

Q

CP

D

Q

CP

D

EXTERNAL REC NETWORK

(RC1 Pin)

REF_SEL

SYNC (1)

SYNC (0)

CHARGE PUMP/LOOP

FILTER

DIVIDE

BY TWO

Q3

Q

CP

D

Q2

Q1

Q0

2x_Q

Q

CP

D

Q

CP

D

Q

Q

CP

D

(

÷1)

(

÷2)

FREQ_SEL

OSCILLATOR

VOLTAGE

CONTROLLED

PHASE/FREQ.

DETECTOR

Reference clock input

Reference clock input

Chooses reference between sync[0] & Sync[1]

Selects Q output frequency

Feedback input to phase detector

Input for external RC network

Clock output (locked to sync)

Inverse of clock output

2 x clock output (Q) frequency (synchronous)

Clock output(Q) frequency

÷ 2 (synchronous)

Indicates phase lock has been achieved (high when locked)

Asynchronous reset (active low)

Disables phase–lock for low freq. testing

Power and ground pins (note pins 8, 10 are

“quiet” supply pins for internal logic only)

Input

Input

Input

Input

Input

Input

Output

Output

Output

Output

Output

Input

Input

1

1

1

1

1

1

5

1

1

1

1

1

1

11

PIN SUMMARY

SYNC[0]

SYNC[1]

REF_SEL

FREQ_SEL

FEEDBACK

RC1

Q(0–4)

Q5

2x_Q

Q/2

LOCK

RST

PLL_EN

VCC,GND

Pin Name

Num

I/O

Function