0930A—04/13/10

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MLF Pin Description (Continued)

PIN #

PIN NAME

TYPE

DESCRIPTION

29

CPUCLKC2_ITP/PCIEXC6

OUT

Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX

output. These are current mode outputs. External resistors are required

for voltage bias. Selected by ITP_EN input.

30

CPUCLKT2_ITP/PCIEXT6

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias. / True clock of

differential PCIEX pair

31

VDDA

PWR

3.3V power for the PLL core.

32

GNDA

PWR

Ground pin for the PLL core.

33

IREF

OUT

This pin establishes the reference current for the differential current-mode

output pairs. This pin requires a fixed precision resistor tied to ground in

order to establish the appropriate current. 475 ohms is the standard value.

34

CPUCLKC1

OUT

Complementary clock of differential pair CPU outputs. These are current

mode outputs. External resistors are required for voltage bias.

35

CPUCLKT1

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

36

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

37

CPUCLKC0

OUT

Complementary clock of differential pair CPU outputs. These are current

mode outputs. External resistors are required for voltage bias.

38

CPUCLKT0

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

39

GND

PWR

Ground pin.

40

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.

41

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

42

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

43

X2

OUT

Crystal output, Nominally 14.318MHz

44

X1

IN

Crystal input, Nominally 14.318MHz.

45

GND

PWR

Ground pin.

46

REF0

OUT

14.318 MHz reference clock.

47

REF1/FSLC/TEST_SEL

I/O

14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency

selection. Refer to input electrical characteristics for Vil_FS and Vih_FS

values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test

Clarification Table

48

CPU_STOP#

IN

Stops all CPUCLK, except those set to be free running clocks

49

PCI/SRC_STOP#

IN

Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0

level, when input low

50

PCICLK2/REQ_SEL**

I/O

3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#

51

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

52

GND

PWR

Ground pin.

53

PCICLK3

OUT

PCI clock output.

54

PCICLK4

OUT

PCI clock output.

55

PCICLK5

OUT

PCI clock output.

56

GND

PWR

Ground pin.