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ICS9EPRS525 Datasheet(PDF) 11 Page - Integrated Device Technology |
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ICS9EPRS525 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 20 page IDTTM 56-pin CK505 for Embedded Intel Systems 1614B—01/21/10 ICS9EPRS525 11 56-pin CK505 for Embedded Systems Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 00 0 0.3V 00 1 0.4V 01 0 0.5V 01 1 0.6V 10 0 0.7V 10 1 0.8V 11 0 0.9V 11 1 1.0V Table 4: Device ID table 000 0 B8b7 B8b6 B8b5 B8b4 Comment 56 pin TSSOP Table 5: Slew Rate Selection Table Bit 1 Bit 0 00 01 10 1 1 1X (2.0 V/ns) Slew Rate HI-Z 0.7X (1.4V/ns) 0.8X (1.6 V/ns) Table 6. PCI3 Configuration Table PCI3_CFG1 (Byte 11, bit 7) PCI3_CFG0 (Byte 11, bit 6) Low 0 or 1 0 0 0 0 = Default Mid 0 or 1 0 1 1 1 High TME=0 1 0 1 2 High TME=1 1 1 1 3 PCI3/CFG0 HW Strap PCI2/TME HW Strap Config Mode Note: 2 bits are needed since CFG0 is tri-level input SRC_Main_SE L (Byte 0, bit 2) Table 7. PLL Modes for PCI3 Configurations Outputs SSC Outputs SSC Outputs SSC 0 = Default CPU/SRC/ PCI Down USB NA - - 100MHz PLL1 (Table 2 applies) 1 CPU Down USB NA SRC/PCI Down 100MHz PLL3 2 CPU Center USB NA SRC/PCI Down 100MHz PLL3 3 CPU Center USB/LAN25 NA SRC/PCI Down 25MHz SE PLL2* *Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18 Config Mode PLL1 PLL2 PLL3 SRC1 PLL Source Table 8. ME Clock Selection Table PCIF5/ ITP_EN iAMT_EN CPU2_AMT_EN CPU1_AMT_EN x1 0 0 x1 0 1 11 1 0 11 1 1 CPU2 = iAMT Clock CPU1 and CPU2 both run in iAMT mode Reserved Description Default, CPU1 = iAMT Clock |
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