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ICS9LPRS502 Datasheet(PDF) 8 Page - Integrated Device Technology

Part # ICS9LPRS502
Description  56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR INTEGRATED SERIES RESISTOR
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS9LPRS502 Datasheet(HTML) 8 Page - Integrated Device Technology

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IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
8
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
15
VDD48
PWR
Power supply for USB clock, nominal 3.3V.
16
USB_48MHz/FSLA
I/O
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
17
GND48
PWR
Ground pin for the 48MHz outputs.
18
VDD96_IO
PWR
Power supply for DOT96 output. 1.05 to 3.3V +/-5%.
19
DOTT_96/SRCT0
OUT
True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be
changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
20
DOTC_96/SRCC0
OUT
Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function
may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
21
GND
PWR
Ground pin for the DOT96 clocks.
22
VDD
PWR
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
23
SRCT1/SE1
OUT
True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5%
downspread. The pin function may be changed via SMBus B1b[4:1]
24
SRCC1/SE2
OUT
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz
SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
25
GND
PWR
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
26
VDDPLL3_IO
PWR
Power supply for PLL3 output. 1.05 to 3.3V +/-5%.
27
SRCT2/SATAT
OUT
True clock of differential SRC/SATA clock pair.
28
SRCC2/SATAC
OUT
Complement clock of differential SRC/SATA clock pair.


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