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9LPRS501YKLFT Datasheet(PDF) 4 Page - Integrated Device Technology |
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9LPRS501YKLFT Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 28 page IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 Advance Information ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR 4 TSSOP Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION 33 SRCT11/CR#_H I/O SRC11 true or Clock Request control H for SRC10 pair The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3 bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10. 34 SRCT10 OUT True clock of differential SRC clock pair. 35 SRCC10 OUT Cpmplement clock of differential SRC clock pair. 36 VDDSRC_IO PWR Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance 37 CPU_STOP#/SRCC5 I/O Stops all CPU Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= CPU_STOP# 1 = SRC5 In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values 38 PCI_STOP#/SRCT5 I/O Stops all PCI Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= PCI_STOP# 1 = SRC5# In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37. 39 VDDSRC PWR VDD pin for SRC internal circuits, 3.3V nominal 40 SRCC6 OUT Complement clock of low power differential SRC clock pair. 41 SRCT6 OUT True clock of low power differential SRC clock pair. 42 GNDSRC PWR Ground for SRC clocks 43 SRCC7/CR#_E I/O SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. 44 SRCT7/CR#_F I/O SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8. 45 VDDSRC_IO PWR Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance 46 CPUC2_ITP/SRCC8 OUT Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# 47 CPUT2_ITP/SRCT8 OUT True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP 48 NC N/A No Connect |
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