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IDT82V3380A Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT82V3380A
Description  SYNCHRONOUS ETHERNET IDT WAN PLL?
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT82V3380A Datasheet(HTML) 7 Page - Integrated Device Technology

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List of Tables
7
May 16, 2011
IDT82V3380A
SYNCHRONOUS ETHERNET WAN PLL™
Table 49: Absolute Maximum Rating ......................................................................................................................................................................... 154
Table 50: Recommended Operation Conditions ........................................................................................................................................................ 154
Table 51: AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 156
Table 52: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 157
Table 53: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 157
Table 54: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 157
Table 55: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 157
Table 56: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 159
Table 57: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 160
Table 58: Output Clock Jitter Generation .................................................................................................................................................................. 162
Table 59: Output Clock Phase Noise ......................................................................................................................................................................... 163
Table 60: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 163
Table 61: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 163
Table 62: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 163
Table 63: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 163
Table 64: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 164
Table 65: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 164
Table 66: Input/Output Clock Timing 3 ...................................................................................................................................................................... 166
Table 67: Output Clock Timing .................................................................................................................................................................................. 168


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