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9ZX21901B Datasheet(PDF) 5 Page - Integrated Device Technology |
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9ZX21901B Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 16 page  IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586J - 12/08/11 9ZX21901B 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 5 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 3.3V Core Supply Voltage VDDA 4.6 V 1,2 3.3V Logic Supply Voltage VDD 4.6 V 1,2 Input Low Voltage VIL GND-0.5 V 1 Input High Voltage VIH Except for SMBus interface VDD+0.5V V 1 Input High Voltage VIHSMB SMBus clock and data pins 5.5V V 1 Storage Temperature Ts -65 150 °C 1 Junction Temperature Tj 125 °C 1 Input ESD protection ESD prot Human Body Model 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Ambient Operating Temperature TCOM Commmercial range 0 70 °C 1 Input High Voltage VIH Single-ended inputs, except SMBus, low threshold and tri-level inputs 2VDD + 0.3 V 1 Input Low Voltage VIL Single-ended inputs, except SMBus, low threshold and tri-level inputs GND - 0.3 0.8 V 1 IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA 1 IINP Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 Fibyp VDD = 3.3 V, Bypass mode 33 400 MHz 2 Fipll VDD = 3.3 V, 100MHz PLL mode 90 100.00 105 MHz 2 Fipll VDD = 3.3 V, 133.33MHz PLL mode 120 133.33 140 MHz 2 Pin Inductance Lpin 7nH 1 CIN Logic Inputs, except DIF_IN 1.5 5 pF 1 CINDIF_IN DIF_IN differential clock inputs 1.5 2.7 pF 1,4 COUT Output pin capacitance 6 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 1.8 ms 1,2 Input SS Modulation Frequency fMODIN Allowable Frequency (Triangular Modulation) 30 33 kHz 1 OE# Latency tLATOE# DIF start after OE# assertion DIF stop after OE# deassertion 1 3 cycles 1,3 Tdrive_PD# tDRVPD DIF output enable after PD# de-assertion 300 us 1,3 Tfall tF Fall time of control inputs 5 ns 1,2 Trise tR Rise time of control inputs 5 ns 1,2 SMBus Input Low Voltage VILSMB 0.8 V 1 SMBus Input High Voltage VIHSMB 2.1 VDDSMB V1 SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V 1 SMBus Sink Current IPULLUP @ VOL 4mA 1 Nominal Bus Voltage VDDSMB 3V to 5V +/- 10% 2.7 5.5 V 1 SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 SMBus Operating Frequency fMAXSMB Maximum SMBus operating frequency 100 kHz 1,5 1Guaranteed by design and characterization, not 100% tested in production. 2Control input must be monotonic from 20% to 80% of input swing. 5The differential input clock must be running for the SMBus to be active Input Current 3Time from deassertion until outputs are >200 mV 4 DIF_IN input Capacitance Input Frequency |
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