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IDT82V3202EDGBLANK Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT82V3202EDGBLANK Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 117 page  List of Tables 6 September 11, 2009 Table 1: Pin Description ............................................................................................................................................................................................. 14 Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 18 Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 19 Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 20 Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 22 Table 6: Input Clock Selection ................................................................................................................................................................................... 23 Table 7: External Fast Selection ................................................................................................................................................................................ 23 Table 8: ‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 24 Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 24 Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 25 Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 25 Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 26 Table 13: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 28 Table 14: T0 DPLL Operating Mode Control ............................................................................................................................................................... 29 Table 15: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 30 Table 16: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 31 Table 17: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 32 Table 18: Holdover Frequency Offset Read ................................................................................................................................................................ 32 Table 19: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 33 Table 20: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 35 Table 21: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 36 Table 22: Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs ..................................................................................................................... 36 Table 23: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL .............................................................................................................................. 37 Table 24: Frame Sync Input Signal Selection .............................................................................................................................................................. 38 Table 25: Synchronization Control ............................................................................................................................................................................... 38 Table 26: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 39 Table 27: Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 40 Table 28: Definition of S/Sr and P Conditions ............................................................................................................................................................. 42 Table 29: Timing Definition for Standard Mode and Fast Mode(1) .............................................................................................................................. 45 Table 30: JTAG Timing Characteristics ....................................................................................................................................................................... 46 Table 31: Register List and Map .................................................................................................................................................................................. 47 Table 32: Power Consumption and Maximum Junction Temperature ......................................................................................................................... 95 Table 33: Thermal Data ............................................................................................................................................................................................... 95 Table 34: Absolute Maximum Rating ........................................................................................................................................................................... 97 Table 35: Recommended Operation Conditions .......................................................................................................................................................... 97 Table 36: CMOS Input Port Electrical Characteristics ................................................................................................................................................. 98 Table 37: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics .................................................................................................. 98 Table 38: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ............................................................................................. 98 Table 39: CMOS Output Port Electrical Characteristics .............................................................................................................................................. 99 Table 40: PECL Output Port Electrical Characteristics .............................................................................................................................................. 100 Table 41: LVDS Output Port Electrical Characteristics .............................................................................................................................................. 101 Table 42: Output Clock Jitter Generation .................................................................................................................................................................. 102 Table 43: Output Clock Phase Noise ......................................................................................................................................................................... 103 Table 44: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 103 Table 45: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 103 Table 46: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 103 Table 47: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 104 List of Tables |
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