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AD9608 Datasheet(PDF) 8 Page - Analog Devices |
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AD9608 Datasheet(HTML) 8 Page - Analog Devices |
8 / 40 page AD9608 Rev. 0 | Page 8 of 40 TIMING SPECIFICATIONS Table 5. Parameter Descriptions Limit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.40 ns typ SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 40 ns min tCLK Period of the SCLK 2 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 10 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns min tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 ns min Timing Diagrams tPD tSKEW tCH tDCO tCLK N – 16 N – 17 N – 1 N + 1 N + 2 N + 3 N + 5 N + 4 N N – 15 N – 14 N – 13 N – 12 VIN CLK+ CLK– CH A/CH B DATA DCOA/DCOB tA Figure 2. CMOS Default Output Mode Data Output Timing tPD tSKEW tCH tDCO tCLK CH A N – 16 CH B N – 15 CH A N – 14 CH B N – 13 CH A N – 12 CH B N – 11 CH A N – 10 CH B N – 9 CH A N – 8 N – 1 N + 1 N + 2 N + 3 N + 5 N + 4 N VIN CLK+ CLK– CH A DATA DCOA/DCOB tA CH B DATA CH B N – 16 CH A N – 15 CH B N – 14 CH A N – 13 CH B N – 12 CH A N – 11 CH B N – 10 CH A N – 9 CH B N – 8 Figure 3. CMOS Interleaved Output Mode Data Output Timing |
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