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AD9648BCPZRL7-125 Datasheet(PDF) 6 Page - Analog Devices |
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AD9648BCPZRL7-125 Datasheet(HTML) 6 Page - Analog Devices |
6 / 44 page AD9648 Rev. 0 | Page 6 of 44 AD9648-105 AD9648-125 Parameter1 Temp Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 98 96 dBc fIN = 30.5 MHz 25°C 90 90 dBc fIN = 70 MHz 25°C 93 91 dBc Full 86 82 dBc fIN = 100 MHz 25°C 92 90 dBc fIN = 200 MHz 25°C 81 84 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −98 −97 dBc fIN = 30.5 MHz 25°C −96 −97 dBc fIN = 70 MHz 25°C −96 −97 dBc Full −91 −90 dBc fIN = 100 MHz 25°C −92 −92 dBc fIN = 200 MHz 25°C −90 −90 dBc TWO-TONE SFDR fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 84 84 dBc CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. AD9628-105/125 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND - 0.3 AVDD + 0.2 V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ LOGIC INPUT (CSB)1 High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF |
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