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A4975 Datasheet(PDF) 5 Page - Allegro MicroSystems |
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A4975 Datasheet(HTML) 5 Page - Allegro MicroSystems |
5 / 13 page Full-Bridge PWM Microstepping Motor Driver A4975 5 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Terminal Functions Terminal Name Description 1 PFD (Percent Fast Decay) The analog input used to set the current-decay mode. 2 REF (VREF) The voltage at this input (along with the value of RS and the states of DAC inputs D0, D1, and D2) set the peak output current. 3 RC The parallel combination of external resistor RT and capacitor CT set the off time for the PWM current regulator. CT also sets the blanking time. 4-5 GROUND Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage measurements. 6 LOGIC SUPPLY (VCC) Supply voltage for the logic circuitry. Typically = 5 V. 7 PHASE The PHASE input determines the direction of current in the load. 8 D2 (DATA2) One-of-three (MSB) control bits for the internal digital-to-analog converter. 9 D1 (DATA1) One-of-three control bits for the internal digital-to-analog converter. 10 OUTA One-of-two output load connections. 11 SENSE Connection to the sink-transistor emitters. Sense resistor RS is connected between this point and ground. 12-13 GROUND Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage measurements. 14 D0 (DATA0) One-of-three (LSB) control bits for the internal digital-to-analog converter. 15 OUTB One-of-two output load connections. 16 LOAD SUPPLY (VBB) Supply voltage for the load. Note the A4975SB (DIP) and the A4975SLB (SOIC) are electrically identical and share a common terminal number assignment. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GROUND GROUND LOGIC SUPPLY PHASE GROUND GROUND RC SENSE D REF LOAD SUPPLY VCC OUTB OUTA VBB LOGIC PFD 1 D0 D 2 |
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