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TSZ02201-0J3J0AJ00180-1-2

©2012 ROHM Co., Ltd. All rights reserved.

11/19

02.MAR.2012 Rev.001

TSZ22111･15･001

BD9141MUV

Datasheet

●Switching Regulator Efficiency

Efficiency ŋ may be expressed by the equation shown below:

Dissipation factors:

1) ON resistance dissipation of inductor and FET：PD(I

2) Gate charge/discharge dissipation：PD(Gate)

3) Switching dissipation：PD(SW)

4) ESR dissipation of capacitor：PD(ESR)

5) Operating current dissipation of IC：PD(IC)

1)PD(I

current.)

2)PD(Gate)=Cgs×f×V

2

(Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)

●Consideration on Permissible Dissipation and Heat Generation

As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is

needed on permissible dissipation or heat generation.

In case of extreme conditions, however, including lower input

voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation

must be carefully considered.

For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.

Because the conduction losses are considered to play the leading role among other dissipation mentioned above including

gate charge/discharge dissipation and switching dissipation.

=0.09375+0.03

=0.12375[Ω]

P=2

With the

consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.

η=

Vin×Iin

×100[%]=

Pin

×100[%]=

×100[%]

Vin

3)PD(SW)=

Fig.27 Thermal derating curve

(VQFN020V4040)

Ambient temperature:Ta [℃]

0

25

50

75

100

125

150

0

2.0

3.0

4.0

②2.21W

①3.56W

1.0

③0.70W

④0.34W

① 4 layers (Copper foil area : 5505mm

copper foil in each layers.

θj-a=35.1℃/W

② 4 layers (Copper foil area : 10.29m

copper foil in each layers.

θj-a=56.6℃/W

③ 4 layers (Copper foil area : 10.29m

θj-a=178.6℃/W

④ IC only.

θj-a=367.6℃/W

105