Atmel AT88SA100S [DATASHEET]

10

8558F

−CRYPTO−9/11

additional leakage on the input circuit of the chip.

5.1.4

Pause State

The pause state is entered via the PauseLong command and can be exited only when the watchdog timer has expired and the

chip transitions to a sleep state. When in the pause state, the chip ignores all transitions on the signal pin but does not enter a

low power consumption mode.

The pause state provides a mechanism for multiple AT88SA100S chips on the same wire to be selected and to exchange data

with the host microprocessor. The PauseLong command includes an optional address field which is compared to the values in

Fuses 84-87. If the two matches, then the chip enters the pause state, otherwise, it continues to monitor the bus for

subsequent commands. The host would selectively put all but one AT88SA100S in the pause state before executing the MAC

command on the active chip. After the end of the watchdog interval all the chips will have entered the sleep state and the

selection process can be started with a Wake token (which will then be honored by all chips) and selection of a subsequent

chip.

5.2

IO Blocks

Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way:

Byte Number

Name

Meaning

0

Count

Number of bytes to be transferred to the chip in the block, including count, packet and checksum,

so this byte should always have a value of (N+1). The maximum size block is 39 and the

minimum size block is four. Values outside this range will cause unpredictable operation.

1 to (N-2)

Packet

Command, parameters and data, or response

See Section 6 for more details

N-1, N

Checksum CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the initial

register value should be zero and after the last bit of the count and packet have been transmitted

the internal CRC register should have a value that matches that in the block. The first byte

transmitted (N-1) is the least significant byte of the CRC value so the last byte of the block is the

most significant byte of the CRC.

5.3

IO Flow

The general IO flow for a MAC command is as follows:

1.

System sends wake token

2.

System sends transmit flag

3.

Receive 0x11 value from the AT88SA100S to verify proper wakeup synchronization

4.

System sends command flag

5.

System sends command block

6.

7.

System sends transmit flag. If command format is OK, the AT88SA100S ignores this flag because the computation

engine is busy. If there was an error, the AT88SA100S responds with an error code

8.

9.

System sends transmit flag

10. Receive output block from the AT88SA100S, system checks CRC

11. If CRC from the AT88SA100S is incorrect, indicating a transmission error, system resends transmit flag

12. System sends sleep flag to the AT88SA100S

All commands other than MAC have a short execution delay. In these cases the system should omit steps six, seven, and