Atmel AT88SC1616C [SUMMARY DATASHEET]

2030LS

−CRYPTO−12/11

3

Figure 1-1.

Block Diagram

Random

Generator

Authentication,

Encryption and

Certification Unit

EEPROM

Answer to Reset

Data Transfer

Password

Verification

Reset Block

Asynchronous

ISO Interface

Synchronous

Interface

Power

Management

V

CC

GND

SCL/CLK

SDA/IO

RST

2.

Pin Descriptions

2.1

2.2

Clock (SCL/CLK)

In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a carrier frequency f. The nominal

length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/f. When the synchronous

protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge clock data out of the

device.

2.3

Reset (RST)

The AT88SC1616C provides an ISO 7816-3 compliant asynchronous answer to reset sequence. When the reset sequence is

activated, the device will output the data programmed into the 64-bit answer-to-reset register. An internal pull-up on the RST

input pad allows the device to be used in synchronous mode without bonding RST. The AT88SC1616C does not support the

synchronous answer-to-reset sequence.

2.4

Serial Data (SDA/IO)

The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of other

this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This rise time will determine

the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while

drawing higher average power. SDA/IO information applies to both asynchronous and synchronous protocols.

When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative

edge clock data out of the device.