Full-Bridge DMOS PWM Motor Driver

A4950

5

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

Device Operation

The A4950 is designed to operate DC motors. The output drivers

nal synchronous rectification to reduce power dissipation. The

current in the output full bridge is regulated with fixed off-time

pulse width modulated (PWM) control circuitry. The IN1 and IN2

inputs allow two-wire control for the bridge.

Protection circuitry includes internal thermal shutdown, and pro-

tection against shorted loads, or against output shorts to ground

or supply. Undervoltage lockout prevents damage by keeping the

outputs off until the driver has enough voltage to operate nor-

mally.

Standby Mode

Low Power Standby mode is activated when both input (INx)

pins are low for longer than 1 ms. Low Power Standby mode

disables most of the internal circuitry, including the charge pump

and the regulator. When the A4950 is coming out of standby

mode, the charge pump should be allowed to reach its regulated

voltage (a maximum delay of 200 μs) before any PWM com-

mands are issued to the device.

Internal PWM Current Control

Initially, a diagonal pair of source and sink FET outputs are

enabled and current flows through the motor winding and the

comparator resets the PWM latch. The latch then turns off the

sink and source FETs (Mixed Decay mode).

The maximum value of current limiting is set by the selection of

tion is approximated by the maximum value of current limiting,

S

the resistance of the sense resistor (Ω) on the LSS terminal.

Overcurrent Protection

A current monitor will protect the IC from damage due to output

shorts. If a short is detected, the IC will latch the fault and disable

the outputs. The fault latch can only be cleared by coming out of

Low Power Standby mode or by cycling the power to VBB. Dur-

ing OCP events, Absolute Maximum Ratings may be exceeded

for a short period of time before the device latches.

Shutdown

If the die temperature increases to approximately 160°C, the full

bridge outputs will be disabled until the internal temperature falls

on VBB to prevent the output drivers from turning-on below the

UVLO threshold.

Braking

The braking function is implemented by driving the device in

Slow Decay mode, which is done by applying a logic high to both

inputs, after a bridge-enable Chop command (see PWM Control

Truth Table). Because it is possible to drive current in both direc-

tions through the DMOS switches, this configuration effectively

shorts-out the motor-generated BEMF, as long as the Chop com-

mand is asserted. The maximum current can be approximated by

ratings of the device are not exceeded in worse case braking situ-

ations: high speed and high-inertia loads.