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ICE3AR4780JZ Datasheet(PDF) 9 Page - Infineon Technologies AG |
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ICE3AR4780JZ Datasheet(HTML) 9 Page - Infineon Technologies AG |
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9 / 34 page  CoolSET®-F3R80 ICE3AR4780JZ Functional Description Version 2.1a 9 11 Jan 2012 Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require re-cycling the AC line. When Active Burst Mode is entered, the internal Bias is switched off most of the time but the Voltage Reference is kept alive in order to reduce the current consumption below 620mA. 3.3 Improved Current Mode Figure 4 Current Mode Current Mode means the duty cycle is controlled by the slope of the primary current. This is done by comparing the FBB signal with the amplified current sense signal. Figure 5 Pulse Width Modulation In case the amplified current sense signal exceeds the FBB signal the on-time ton of the driver is finished by resetting the PWM-Latch (Figure 5). The primary current is sensed by the external series resistor RSense inserted in the source of the integrated CoolMOS®. By means of Current Mode regulation, the secondary output voltage is insensitive to the line variations. The current waveform slope will change with the line variation, which controls the duty cycle. The external RSense allows an individual adjustment of the maximum source current of the integrated CoolMOS®. To improve the Current Mode during light load conditions the amplified current ramp of the PWM-OP is superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (see Figure 6). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by VOSC. When the oscillator triggers the Gate Driver, T2 is opened so that the voltage ramp can start. Figure 6 Improved Current Mode In case of light load the amplified current ramp is too small to ensure a stable regulation. In that case the Voltage Ramp is a well defined signal for the comparison with the FBB-signal. The duty cycle is then controlled by the slope of the Voltage Ramp. By means of the time delay circuit which is triggered by the inverted VOSC signal, the Gate Driver is switched-off until it reaches approximately 156ns delay time (Figure x3.25 PWM OP Improved Current Mode 0.6V C8 PWM-Latch CS FBB R S Q Q Driver Soft-Start Comparator t FBB Amplified Current Signal ton t 0.6V Driver PWM OP 0.6V 10k Oscillator C8 T2 R1 FBB PWM-Latch V1 Gate Driver Voltage Ramp VOSC Soft-Start Comparator time delay circuit (156ns) X3.25 PWM Comparator |
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