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SX1508B Datasheet(PDF) 9 Page - Semtech Corporation |
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SX1508B Datasheet(HTML) 9 Page - Semtech Corporation |
9 / 37 page ADVANCED COMMUNICATIONS & SENSING Rev 4 – 26 th April 2011 9 www.semtech.com SX1508B/SX1509B World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine Symbol Description Conditions Min Typ Max Unit fSCL SCL clock frequency - - - 400 kHz tHD;STA Hold time (repeated) START condition - 0.6 - - µs tLOW LOW period of the SCL clock - 1.3 - - µs tHIGH HIGH period of the SCL clock - 0.6 - - µs tSU;STA Set-up time for a repeated START condition - 0.6 - - µs tHD;DAT Data hold time - 0 (4) - 0.9 (5) µs tSU;DAT Data set-up time - 100 (6) - - ns tr Rise time of both SDA and SCL - 20+0.1Cb (7) - 300 ns tf Fall time of both SDA and SCL - 20+0.1Cb (7) - 300 ns tSU;STO Set-up time for STOP condition - 0.6 - - µs tBUF Bus free time between a STOP and START condition - 1.3 - - µs Cb Capacitive load for each bus line - - - 400 pF VnL Noise margin at the LOW level for each connected device (including hysteresis) - - 0.1* VDDM - V VnH Noise margin at the HIGH level for each connected device (including hysteresis) - - 0.2* VDDM - V tSP Pulse width of spikes suppressed by the input filter - - - 50 ns Miscellaneous RPULL Programmable pull-up/down resistors for IO[0-7] - - 42 - k Internal 1.3 2 2.6 fOSC Oscillator frequency External from OSCIN (40-60% duty cycle) - - 2.6 MHz (1) Assuming no load connected to outputs and inputs fixed to VCC1,2 or GND. (2) Can be increased by tying together and driving simultaneously several I/Os. (3) All values referred to VIHMR min and VILM max levels. (4) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to VIHMR min) to bridge the undefined region of the falling edge of SCL. (5) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. (6) A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t SU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max+ tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. (7) Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed. (8) With RegHighInput bit enabled (VCCx min =1.65V), else 3.6V (VCCx min = 1.2V) Table 5 – Electrical Specifications |
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