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ADVANCED COMMUNICATIONS & SENSING

DATASHEET

SX8122

1V Motor/LED timer

ACS - Revision 2.2

August 2010

© Semtech Corp.

TECHNICAL DESCRIPTION

4

System architecture

4.1

SX8122 architecture

The system is based on the cyclic acquisition of the TRIGGER and VDD voltages.

4.2

SX8122 timer behavior

The SX8122 has an internal level detector that compares the TRIGGER volatge to the VDD voltage. When

TRIGGER is above 2/3 of VDD, the comparator sets its output to high; when the TRIGGER is below 1/3 of VDD,

the comparator sets its output to low. As long as the TRIGGER voltage is between 1/3 VDD and 2/3 VDD, the

comparator output remains unchanged.

Figure 2. SX8122 Architecture

R

S

Q

Q

2/3 VDD

1/3 VDD

VDD

VSS

1.41V

BURST

VDD

VDD

TRIGGER

DISCHARGE

CHARGE

NIMH

MOTOR

VSS

LED