MCM56824A

2

MOTOROLA FAST SRAM

BLOCK DIAGRAM

Q

0

1

INPUT

DATA

CONTROL

(MSB)

(LSB)

V/S

A9

A6

DQ23

MEMORY ARRAY

512 ROWS x

384 COLUMNS

ROW

DECODER

COLUMN DECODER

COLUMN I/O

VCC

A11

A10

A5

A0

A12

X/Y

G

W

E1

E2

DQ0

A12

2 TO 1 MUX

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

VSS

TRUTH TABLE

E1

E2

G

W

V/S

Mode

Supply

Current

I/O

Status

H

X

X

X

X

Not Selected

ISB

High–Z

X

L

X

X

X

Not Selected

ISB

High–Z

L

H

H

H

X

Output Disable

ICC

High–Z

L

H

L

H

H

Read Using X/Y

ICC

Data Out

L

H

L

H

L

Read Using A12

ICC

Data Out

L

H

X

L

H

Write Using X/Y

ICC

Data In

L

H

X

L

L

Write Using A12

ICC

Data In

NOTE: X=don’t care.

Rating

Symbol

Value

Unit

Power Supply Voltage

VCC

– 0.5 to + 7.0

V

Voltage Relative to VSS for Any Pin

Except VCC

Vin, Vout

– 0.5 to VCC + 0.5

V

Output Current (per I/O)

Iout

± 20

mA

Power Dissipation

PD

1.75

W

Temperature Under Bias

Tbias

– 10 to + 85

°C

Operating Temperature

TA

0 to + 70

°C

Storage Temperature

Tstg

– 55 to + 125

°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could affect device reliability.

This device contains circuitry to protect

against damage due to high static voltages

or electric fields; however, it is advised that

normal precautions be taken to avoid appli-

cation of any voltage higher than maximum

rated voltages to this high–impedance

circuit.

This CMOS memory circuit has been de-

signed to meet the dc and ac specifications

shown in the tables, after thermal equi-

librium has been established. The circuit is

assumed to be in a test socket or mounted

on a printed circuit board with at least 300

LFPM

of

transverse

air

flow

being

maintained.