R2A20162NS/SA/SP

New Product

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R03DS0016EJ0100 Rev.1.00

2011.09.05

Pin Description

Pin Arrangement

R2A20162NS (Top view)

R2A20162SA/SP (Top view)

1

2

3

4

8

7

6

5

Ao1

Ao2

N.C.

Vcc

LD

CLK

DI

GND

Outline: PRSP0008DE-C [SP]

PTSP-0008JC-B [SA]

1

2

3

4

8

7

6

5

Ao1

Ao2

N.C.

Vcc

LD

CLK

DI

GND

N.C.: Not connected

Outline: PWSN0008KA-A [NS]

GND terminal

GND

5

Power supply terminal

Vcc

4

Not connected

N.C.

3

A02

2

8-bit resolution D/A converter output terminals

(After power-on, all channels are reset and DAC data 00h is output.)

Ao1

1

Load terminal

(When High level is input to LD terminal, value in 10-bit shift register is

loaded into decoder and 8-bit latch.)

LD

8

Serial clock input terminal

(Input signal from DI terminal is input to 10-bit shift register at rise of serial

clock.)

CLK

7

Serial data input terminal.

(Input serial data with a 10-bit data length.)

DI

6

Function

Pin Name

Pin No.

N.C.: Not connected