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SAB-C505C-2RM Datasheet(PDF) 11 Page - Siemens Semiconductor Group |
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SAB-C505C-2RM Datasheet(HTML) 11 Page - Siemens Semiconductor Group |
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11 / 85 page  Semiconductor Group 11 1997-12-01 C505 / C505C C505A / C505CA P2.0-P2.7 18-25 I/O Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors. PSEN 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. ALE 27 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periods except during an external data memory access. When instructions are executed from internal ROM or OTP (EA=1) the ALE generation can be disabled by bit EALE in SFR SYSCON. ALE should not be driven during reset operation. *) I = Input O = Output Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function |
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