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R5F56307CDFN Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R5F56307CDFN Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 165 page  R01DS0060EJ0100 Rev.1.00 Page 11 of 168 Sep 13, 2011 RX630 Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram. Figure 1.2 Block Diagram ICUb: Interrupt control unit DTCa: Data transfer controller DMACA: DMA controller BSC: Bus controller WDTA: Watchdog timer IWDTa: Independent watchdog timer CRC: CRC (cyclic redundancy check) calculator SCIc, SCId: Serial communications interface USBa: USB 2.0 function module RSPI: Serial peripheral interface CAN: CAN module MTU2a: Multi-function timer pulse unit 2 POE2a: Port output enable 2 TPUA: 16-bit timer pulse unit PPG: Programmable pulse generator TMR: 8-bit timer CMT: Compare match timer RTCa: Realtime clock RIIC: I 2C bus interface IEB: IEBus controller External bus BSC Clock generation circuit RX CPU RAM ROM Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C 10-bit ADC × 8 channels 12-bit ADC × 21 channels MTU2a × 6 channels (unit 0) 10-bit DAC × 2 channels SCIc × 12 channels WDTA RIIC × 4 channels E2 DataFlash CRC IWDTa USBa (1 port) CAN × 3 channels RTCa POE2a TPUa × 6 channels (unit 1) IEB CMT × 2 channels (unit 1) CMT × 2 channels (unit 0) TMR × 2 channels (unit 1) TMR × 2 channels (unit 0) PPG (unit 1) PPG (unit 0) RSPI (unit 1) RSPI (unit 0) DTCa DMACA × 4 channels ICUb Temperature sensor TPUa × 6 channels (unit 0) RSPI (unit 2) SCId × 1 channel Port D Port E Port F Port G Port H Port J Port K Port L |
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